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Sitronix
n INTRODUCTION
2
ST7588T
81 x 132 Dot Matrix LCD Controller/Driver
ST7588T is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 132-segment, 80-common and 1-icon driver circuits. ST7588T can be connected directly to a microprocessor which accepts parallel interface (8-bit), serial peripheral interface (3-line or 4-line SPI), I C interface. Display data stores in an on-chip display data RAM (DDRAM) of 81 x 132 bits. It performs display data RAM read/write operation without external operating clock to minimize the power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components.
n FEATURES
Single-chip LCD controller & driver Driver Output Circuits O O O O O O O O O O O 132-segment / 81-common (1/81 duty) Optional display duty 1/49, 1/65 and 1/81 (selected by MODE[1:0] pin) Partial display mode: 1/33 duty and 1/17 duty O O Capacity: 81X132=10,692 bits 8-bit parallel bi-directional interface supports 6800-series or 8080-series MPU 4-line A mode SPI (write only) 4-line B mode SPI (write only) 3-line 8-bit A mode SPI (write only) 3-line 8-bit B mode SPI (write only) 3 line 9-bit SPI (write only) I C (Inter-Integrated Circuit) Interface (write only)
2
On-chip Low Power Analog Circuit O O O Built-in Voltage Booster (x2, x3, x4, x5, x6) Support external booster supply (VOUT) Built-in Voltage Regulator With 255-step electronic contrast control (temperature gradient -0.12%/C) Built-in Voltage Follower (with 1/4 ~ 1/11 bias) Supports external power supply circuits
On-chip Display Data RAM Microprocessor Interface
External RESB (hardware reset) Pin Built-in Oscillation Circuit O O O O Oscillator requires no external components VDD1: 1.8V to 3.3V (typ.) VDD2: 2.4V to 3.3V (typ.) Recommend LCD Vop: 9.5V ~ 10.5V (1/10 Bias, 1/81 Duty) Temperature Range: -30 to +85 C Wide Voltage Range
ST7588T
6800, 8080, 4-Line, 3-Line interface (without I2C interface) I2C interface
ST7588Ti
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. Ver 1.3 1/61 2007/09/20
ST7588T
n PAD ARRANGEMENT (COG)
Chip Size: 7,708 m x 980 m Bump Pitch: (minimum) PAD NO 1~185, 248~276: 45m (COM/SEG) PAD NO 186~187, 188~189, 191~192, 193~194, 195~196, 197~198, 199~200, 201~202, 213~214,215~216: 119m PAD NO 187~188, 189~190, 192~193, 194~195, 196~197, 198~199, 200~201, 209~211, 212~213, 214~215, 216~217, 218~220: 73m PAD NO 190~191: 134m; PAD NO 220~221: 93m; Bump Size: PAD NO 1~156, 174~185, 248~259: 30(x) m x 80(y) m PAD NO 157~173, 260~276: 80(x) m x 30(y) m PAD NO 186~202, 209~247: 55(x) m x 60(y) m PAD NO 203~208: 45(x) m x 60(y) m Bump Height: 17 m Chip Thickness: 480 m PAD NO 202~203: 77m; PAD NO 208~209: 68m; PAD NO 204~205, 206~207: 75m PAD NO 211~212, 217~218: 102m PAD NO 243~244: 145m PAD NO 221~243, 244~247: 70m PAD NO 203~204, 205~206: 175m; PAD NO 207~208: 150m;
Ver 1.3
2/61
2007/09/20
ST7588T
n PAD CENTER COORDINATES (49 duty)
Pad No. 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 032 033 034 035 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123] SEG[122] SEG[121] SEG[120] SEG[119] SEG[118] SEG[117] SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109] X 3487 3442 3397 3352 3307 3262 3217 3172 3127 3082 3037 2992 2947 2902 2857 2812 2767 2722 2677 2632 2587 2542 2497 2452 2407 2362 2317 2272 2227 2182 2137 2092 2047 2002 1957 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 Pad No. 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 061 062 063 064 065 066 067 068 069 070 Pin Name SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] X 1912 1867 1822 1777 1732 1687 1642 1597 1552 1507 1462 1417 1372 1327 1282 1237 1192 1147 1102 1057 1012 967 922 877 832 787 742 697 652 607 562 517 472 427 382 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379
Ver 1.3
3/61
2007/09/20
ST7588T
Pad No. 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 100 101 102 103 104 105 106 Pin Name SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] X 337 292 247 202 157 112 67 22 -23 -68 -113 -158 -203 -248 -293 -338 -383 -428 -473 -518 -563 -608 -653 -698 -743 -788 -833 -878 -923 -968 -1013 -1058 -1103 -1148 -1193 -1238 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 Pad No. 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Pin Name SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] X -1283 -1328 -1373 -1418 -1463 -1508 -1553 -1598 -1643 -1688 -1733 -1778 -1823 -1868 -1913 -1958 -2003 -2048 -2093 -2138 -2183 -2228 -2273 -2318 -2363 -2408 -2453 -2498 -2543 -2588 -2633 -2678 -2723 -2768 -2813 -2858 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379
Ver 1.3
4/61
2007/09/20
ST7588T
Pad No. 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 Pin Name SEG[1] SEG[0] COMS1 COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved X -2903 -2948 -2993 -3038 -3083 -3128 -3173 -3218 -3263 -3308 -3353 -3398 -3443 -3488 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3488 -3443 -3398 -3353 -3308 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 358 313 268 223 178 133 88 43 -2 -47 -92 -137 -182 -227 -272 -317 -362 -379 -379 -379 -379 -379 Pad No. 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved SYNC CL DOF CSB VSS RESB A0 /WR(R/W) /RD(E) D0 D1 D2 D3 D4 D5 D6 D7 T5 T4 T3 T2 T1 T0 VSS VSS VSS MS MODE0 MODE1 X -3263 -3218 -3173 -3128 -3083 -3038 -2993 -2417 -2298 -2225 -2106 -2033 -1899 -1780 -1707 -1588 -1515 -1396 -1323 -1204 -1131 -1012 -939 -820 -743 -568 -493 -318 -243 -93 -25 48 121 223 296 415 Y -379 -379 -379 -379 -379 -379 -379 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389
Ver 1.3
5/61
2007/09/20
ST7588T
Pad No. 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Pin Name PS0 PS1 PS2 VDD1 VDD1 VDD1 VDD2 VDD2 VOUT VOUT VOUT CAP3N CAP3N CAP3P CAP3P CAP5P CAP5P CAP1N CAP1N CAP1P CAP1P CAP2P CAP2P CAP2N CAP2N CAP4P CAP4P VRS V0 V1 V2 X 488 607 680 782 855 928 1021 1091 1161 1231 1301 1371 1441 1511 1581 1651 1721 1791 1861 1931 2001 2071 2141 2211 2281 2351 2421 2491 2561 2706 2776 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 Pad No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 Pin Name V3 V4 COMS2 COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] COM[35] COM[34] COM[33] COM[32] COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] COM[25] COM[24] Reserved Reserved Reserved Reserved X 2846 2916 2992 3037 3082 3127 3172 3217 3262 3307 3352 3397 3442 3487 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 Y -389 -389 -379 -379 -379 -379 -379 -379 -379 -379 -379 -379 -379 -379 -362 -317 -272 -227 -182 -137 -92 -47 -2 43 88 133 178 223 268 313 358
Ver 1.3
6/61
2007/09/20
ST7588T
n PAD CENTER COORDINATES (65 duty)
Pad No. 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 032 033 034 035
Pin Name COM[35] COM[34] COM[33] COM[32] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123] SEG[122] SEG[121] SEG[120] SEG[119] SEG[118] SEG[117] SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109]
X 3487 3442 3397 3352 3307 3262 3217 3172 3127 3082 3037 2992 2947 2902 2857 2812 2767 2722 2677 2632 2587 2542 2497 2452 2407 2362 2317 2272 2227 2182 2137 2092 2047 2002 1957
Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379
Pad No. 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 061 062 063 064 065 066 067 068 069 070
Pin Name SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74]
X 1912 1867 1822 1777 1732 1687 1642 1597 1552 1507 1462 1417 1372 1327 1282 1237 1192 1147 1102 1057 1012 967 922 877 832 787 742 697 652 607 562 517 472 427 382
Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379
Ver 1.3
7/61
2007/09/20
ST7588T
Pad No. 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 100 101 102 103 104 105 106 Pin Name SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] X 337 292 247 202 157 112 67 22 -23 -68 -113 -158 -203 -248 -293 -338 -383 -428 -473 -518 -563 -608 -653 -698 -743 -788 -833 -878 -923 -968 -1013 -1058 -1103 -1148 -1193 -1238 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 Pad No. 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Pin Name SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] X -1283 -1328 -1373 -1418 -1463 -1508 -1553 -1598 -1643 -1688 -1733 -1778 -1823 -1868 -1913 -1958 -2003 -2048 -2093 -2138 -2183 -2228 -2273 -2318 -2363 -2408 -2453 -2498 -2543 -2588 -2633 -2678 -2723 -2768 -2813 -2858 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379
Ver 1.3
8/61
2007/09/20
ST7588T
Pad No. 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 Pin Name SEG[1] SEG[0] COMS1 COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] Reserved X -2903 -2948 -2993 -3038 -3083 -3128 -3173 -3218 -3263 -3308 -3353 -3398 -3443 -3488 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3488 -3443 -3398 -3353 -3308 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 358 313 268 223 178 133 88 43 -2 -47 -92 -137 -182 -227 -272 -317 -362 -379 -379 -379 -379 -379 Pad No. 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved SYNC CL DOF CSB VSS RESB A0 /WR(R/W) /RD(E) D0 D1 D2 D3 D4 D5 D6 D7 T5 T4 T3 T2 T1 T0 VSS VSS VSS MS MODE0 MODE1 X -3263 -3218 -3173 -3128 -3083 -3038 -2993 -2417 -2298 -2225 -2106 -2033 -1899 -1780 -1707 -1588 -1515 -1396 -1323 -1204 -1131 -1012 -939 -820 -743 -568 -493 -318 -243 -93 -25 48 121 223 296 415 Y -379 -379 -379 -379 -379 -379 -379 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389
Ver 1.3
9/61
2007/09/20
ST7588T
Pad No. 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Pin Name PS0 PS1 PS2 VDD1 VDD1 VDD1 VDD2 VDD2 VOUT VOUT VOUT CAP3N CAP3N CAP3P CAP3P CAP5P CAP5P CAP1N CAP1N CAP1P CAP1P CAP2P CAP2P CAP2N CAP2N CAP4P CAP4P VRS V0 V1 V2 X 488 607 680 782 855 928 1021 1091 1161 1231 1301 1371 1441 1511 1581 1651 1721 1791 1861 1931 2001 2071 2141 2211 2281 2351 2421 2491 2561 2706 2776 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 Pad No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 Pin Name V3 V4 COMS2 COM[63] COM[62] COM[61] COM[60] COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] X 2846 2916 2992 3037 3082 3127 3172 3217 3262 3307 3352 3397 3442 3487 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 Y -389 -389 -379 -379 -379 -379 -379 -379 -379 -379 -379 -379 -379 -379 -362 -317 -272 -227 -182 -137 -92 -47 -2 43 88 133 178 223 268 313 358
Ver 1.3
10/61
2007/09/20
ST7588T
n PAD CENTER COORDINATES (81 duty)
Pad No. 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 032 033 034 035
Pin Name COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123] SEG[122] SEG[121] SEG[120] SEG[119] SEG[118] SEG[117] SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109]
X 3487 3442 3397 3352 3307 3262 3217 3172 3127 3082 3037 2992 2947 2902 2857 2812 2767 2722 2677 2632 2587 2542 2497 2452 2407 2362 2317 2272 2227 2182 2137 2092 2047 2002 1957
Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379
Pad No. 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 061 062 063 064 065 066 067 068 069 070
Pin Name SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74]
X 1912 1867 1822 1777 1732 1687 1642 1597 1552 1507 1462 1417 1372 1327 1282 1237 1192 1147 1102 1057 1012 967 922 877 832 787 742 697 652 607 562 517 472 427 382
Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379
Ver 1.3
11/61
2007/09/20
ST7588T
Pad No. 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 100 101 102 103 104 105 106 Pin Name SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] X 337 292 247 202 157 112 67 22 -23 -68 -113 -158 -203 -248 -293 -338 -383 -428 -473 -518 -563 -608 -653 -698 -743 -788 -833 -878 -923 -968 -1013 -1058 -1103 -1148 -1193 -1238 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 Pad No. 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Pin Name SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] X -1283 -1328 -1373 -1418 -1463 -1508 -1553 -1598 -1643 -1688 -1733 -1778 -1823 -1868 -1913 -1958 -2003 -2048 -2093 -2138 -2183 -2228 -2273 -2318 -2363 -2408 -2453 -2498 -2543 -2588 -2633 -2678 -2723 -2768 -2813 -2858 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379 379
Ver 1.3
12/61
2007/09/20
ST7588T
Pad No. 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 Pin Name SEG[1] SEG[0] COMS1 COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] COM[32] X -2903 -2948 -2993 -3038 -3083 -3128 -3173 -3218 -3263 -3308 -3353 -3398 -3443 -3488 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3743 -3488 -3443 -3398 -3353 -3308 Y 379 379 379 379 379 379 379 379 379 379 379 379 379 379 358 313 268 223 178 133 88 43 -2 -47 -92 -137 -182 -227 -272 -317 -362 -379 -379 -379 -379 -379 Pad No. 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 Pin Name COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] COM[39] SYNC CL DOF CSB VSS RESB A0 /WR(R/W) /RD(E) D0 D1 D2 D3 D4 D5 D6 D7 T5 T4 T3 T2 T1 T0 VSS VSS VSS MS MODE0 MODE1 X -3263 -3218 -3173 -3128 -3083 -3038 -2993 -2417 -2298 -2225 -2106 -2033 -1899 -1780 -1707 -1588 -1515 -1396 -1323 -1204 -1131 -1012 -939 -820 -743 -568 -493 -318 -243 -93 -25 48 121 223 296 415 Y -379 -379 -379 -379 -379 -379 -379 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389
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Pad No. 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Pin Name PS0 PS1 PS2 VDD1 VDD1 VDD1 VDD2 VDD2 VOUT VOUT VOUT CAP3N CAP3N CAP3P CAP3P CAP5P CAP5P CAP1N CAP1N CAP1P CAP1P CAP2P CAP2P CAP2N CAP2N CAP4P CAP4P VRS V0 V1 V2 V3 V4 COMS2 COM[79] COM[78] X 488 607 680 782 855 928 1021 1091 1161 1231 1301 1371 1441 1511 1581 1651 1721 1791 1861 1931 2001 2071 2141 2211 2281 2351 2421 2491 2561 2706 2776 2846 2916 2992 3037 3082 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -379 -379 -379 Pad No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 Pin Name COM[77] COM[76] COM[75] COM[74] COM[73] COM[72] COM[71] COM[70] COM[69] COM[68] COM[67] COM[66] COM[65] COM[64] COM[63] COM[62] COM[61] COM[60] COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] X 3127 3172 3217 3262 3307 3352 3397 3442 3487 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 3743 Y -379 -379 -379 -379 -379 -379 -379 -379 -379 -362 -317 -272 -227 -182 -137 -92 -47 -2 43 88 133 178 223 268 313 358
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n BLOCK DIAGRAM
Figure 1
Block diagram
Ver 1.3
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ST7588T
n PIN DESCRIPTIONS
LCD driver outputs Pin Name Type Description LCD segment driver outputs The display data and frame signal control the output voltage of segment driver. Display data SEG0 to SEG131 O 1 1 0 0 Frame Negative Positive Negative Positive Segment Driver Output Normal Display Reverse Display V0 VSS V2 V3 VSS V2 V3 V0 VSS VSS 132 No. of Pins
Display OFF, Power save mode
LCD column driver outputs The scan signal and frame signal control the output voltage of common driver. Display data COM0 to COM79 O 1 1 0 0 Frame Negative Positive Negative Positive Common Driver Output Normal Display Reverse Display VSS V0 V1 V4 VSS 80
Display OFF, Power save mode COMS1 COMS2 Pin Name O
Common output for the icons. COMS1 and COMS2 are identical. The output signals of these pins are same. If not using, they should be left open. Description Microprocessor interface selection pins Interface Mode PS2 PS1 PS0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 8-bit 8080 parallel interface 8-bit 6800 parallel interface 4-line serial interface A mode 4-line serial interface B mode 3-line (8 bit) serial interface A mode 3-line (8-bit) serial interface B mode 3-line (9-bit) serial interface I2C serial interface
2
MICROPROCESSOR INTERFACE Type No. of Pins
PS[2:0]
I
0 1 0 1 0 1
3
CSB
I
Chip select input pin Microprocessor Interface is enabled only when CSB is "L". When chip select is non-active (CSB="H"), D[7:0] are high impedance. CSB is not used in I2C interface. Fix this pin to "H" by VDD1. Reset input pin When RESB is "L", initialization is executed. It determines whether the data bits are data or a command. A0= "H" : Indicates that D[7:0] are display data. A0= "L" : Indicates that D[7:0] are control data. A0 is not used in 3-line SPI or I2C interface. Fix this pin to "H" by VDD1.
1
RESB
I
1
A0
I
1
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Pin Name Type Description Read/Write execution control pin : (when PS[1:0]=L,L) Description PS2 MPU type /WR(R/W) H /WR(R/W) I L 8080-series /WR 6800-series R/W Read/Write control input pin. R/W="H": read R/W="L": write Write enable clock input pin. The data on D0 to D7 are latched at the rising edge of the /WR signal. No. of Pins
1
This pin is not used in the serial interface. Fix to "H" by VDD1. Read/Write execution control pin : (when PS[1:0]=L,L) PS2 MPU Type /RD (E) Description Enable control input pin. R/W="H": When E is "H", D0 to D7 are in an H 6800-series E output status. R/W="L": The data on D0 to D7 are latched at the falling edge of the E signal. Read enable clock input pin L 8080-series /RD When /RD is "L", D0 to D7 are in an output status. This pin is not used in the serial interface. Fix to "H" by VDD1. When using parallel interface: 8-bit interface This is an 8-bit bi-directional data bus that connected to the standard 8-bit microprocessor data bus. When chip select pin (CSB) is not active, D7 to D0 are high impedance. When using serial interface: 3-line or 4-line D0: serial input clock (SCL). D1 to D3: serial input data (SDA). D4, D5, D6, D7: fix to "H" by VDD1. When chip select pin (CSB) is not active, D7 to D0 are high impedance. 2 When using I C interface (PS[2:0]="H") D0: SCL, serial clock input. D1: SDA_IN, serial input data. 2 D2 to D5: SDA_OUT, serial data acknowledge for the I C interface. D6 and D7 are slave address bit 0 and 1 which can be set as 00 to 11. D1 to D5 must be connected together (SDA) Chip select pin (CSB) is not used and must be fixed to "H" by VDD1. By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully I C interface compatible. Separating acknowledge output from the serial data input is advantageous for chip-on-glass (COG) applications. In COG applications, the ITO resistance and the pull-up resistor will form a voltage divider which affects acknowledge-signal level. Larger ITO resistance will raise the acknowledge-signal level and system cannot recognize this level as a valid logical "0" level. By splitting SDA_IN from SDA_OUT, the IC can be used in a mode which ignores the acknowledge-bit. For applications that check the acknowledge-bit, it is important to minimize the ITO resistance of the SDA_OUT trace to guarantee a valid low level.
2
/RD (E)
I
1
D[7:0]
I/O
8
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Pin Name Type Description Use this pin can select 1/49 duty, 1/65duty or 1/81 duty mode Mode0 Duty Mode1 MODE[1:0] I 0 0 1 1 Power Supply Pins Pin Name VSS VDD1 Type Description No. of Pins 9 5 Power Ground. Digital Supply Voltage. Power The 2 supply rails VDD1 and VDD2 could be connected together. If Digital Option pin is high, must be this level. Analog Supply Voltage. The 2 supply rails VDD1 and VDD2 could be connected together. If using external voltage generator, the external supply voltage should connect to Power VOUT pad as an external voltage input. VOUT must series one capacitor to VDD2. Power 0 1 0 1 1/49 duty 1/65 duty --1/81 duty 1 No. of Pins
VDD2
4
VOUT
3
V0, This is a multi-level power supply for the liquid crystal operation. Power V1, V2, V3, V4 VOUT V0 V1 V2 V3 V4 VSS Voltage Regulator reference level. VRS Power This pin must be left open. Test Pin Pin Name T0~T5 MS SYNC /DOF CL Type Test I O Description These pins are reserved for test only. Please fix this pin to "H" by VDD1. Please let these pads floating.
5 1
No. of Pins 6 1 1 1 1
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ITO Limitations
PIN Name T0~5, SYNC, /DOF, CL VDD1, VDD2, VSS, VOUT V0, V1, V2, V3, V4, CAP1P, CAP1N, CAP2P, CAP2N , CAP3P, CAP3N, CAP4P, CAP5P D[5:1] (if using I C interface mode) CSB, E, R/W, A0, D[7:0] PS[2:0], MODE[1:0], MS RESB Note: 1. 2. The option setting to be "H" should connect to VDD1. The option setting to be "L" should connect to VSS1.
2
ITO Resistance Floating <100 <200 <300 <1K < 5K <10K
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n FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
CSB pin is used as chip-select input. ST7588T can interface with an MPU when CSB is "L". When CSB is "H", the pins of A0, /RD (E), and /WR(R/W) with any combination will be ignored and D[7:0] are high impedance. In 3-line and 4-line serial interfaces, the internal shift-register and bit-counter are reset when CSB is "H".
Interface Selection
ST7588T has eight types of interface for all kinds of MPU (6 kinds of serial interface and 2 kinds of parallel interface). The selection among these interfaces uses PS[2:0] pins as shown in Table 1. Table 1 Type Parallel PS2 0 1 0 1 Serial 0 1 0 1 PS1 0 0 1 1 0 0 1 1 Parallel / Serial Interface Mode PS0 0 0 0 0 1 1 1 1 Interface mode 8bit 8080-series MPU mode 8 bit 6800-series MPU mode 4-line serial interface A mode 4-line serial interface B mode 3-line (8 bit) serial interface A mode 3-line (8-bit) serial interface B mode 3-line (9-bit) serial interface 2 I C serial interface
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS0 as shown in Table 2. The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in Table 3. Table 2 PS2 H L Common A0 H H L L CSB CSB CSB 6800-series E_RD (E) H H H H RW_WR (RW) H L H L Microprocessor Selection for Parallel Interface A0 A0 A0 Table 3 E_RD E /RD 8080-series E_RD (/RD) L H L H RW_WR (/WR) H L H L Display data read out Display data write Register status read Writes to internal register (instruction) Description RW_WR RW /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Parallel Data Transfer
NOTE: In 6800-series interface mode, fixing E_RD pin at "H" can use CSB as enable signal instead. In this case, the interface data is latched at the rising edge of CSB and the access type of this transfer is determined by signals at A0 and RW_WR as defined in 6800-series mode.
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Serial Interface
4-Line SPI When the ST7588T is active (CSB="L"), serial data (DB1~3) and serial clock (DB0) inputs are enabled. While not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either by software or the Register Select (A0) Pin. When the A0 pin is used, data is display data when A0 is high and is command data when A0 is low. When A0 is not used, the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data Direction command (11101000) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are sent, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data. (1) 4-Line SPI A Mode (PS0 = "L", PS1 = "H", PS2 = "L")
Figure 2
4-Line SPI Timing
(2) 4-Line SPI B Mode (PS0 = "L", PS1 = "H", PS2 = "H")
Figure 3
4Lline SPI Timing
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3-Line SPI (1) 3-Line (8 bit) SPI In this mode, the default transfer type is command. Two kinds of parameters must be set before write data: start addresses and data length. The flow to write data is: (1) Set start addresses, (2) Set data length and (3) Transfer data. Each bit is latched at the rising edge of SCL. The column address pointer is automatically increased by 1 after receiving 1 byte data.
Flow 1
Instruction Set Page Address Set Column Address (H) Set Column Address (L) Set No. of Data Bytes (H) Set No. of Data Bytes (M)
0 1 1 0 0
1 1 1 1 1
Bit Order (Left --> Right) 0 0 Y3 Y2 1 1 X7 X6 1 1 1 0 1 0
Y1 X5
Y0 X4 X0 DA8 DA4 DA0
2 3
X2 X1 X3 0 DA10 DA9 DA7 DA6 DA5 DA1
Set No. of Data Bytes (L) & Start 0 1 0 1 DA3 DA2 Transfer Data bytes Figure 4 3-line (8 bit) SPI A mode Timing (A0 is not used)
Flow 1
Instruction Set Page Address Set Column Address (H) Set Column Address (L) Set No. of Data Bytes (H) Set No. of Data Bytes (M)
Y0 X4 X0 DA8 DA4
Y1 X5
Bit Order (Left --> Right) Y2 Y3 0 0 X6 X7 1 1 0 1 0 1 1 1
1 1 1 1 1 1
0 1 1 0 0 0
2 3
X1 X2 X3 DA9 DA10 0 DA5 DA6 DA7
Set No. of Data Bytes (L) & Start DA0 DA1 DA2 DA3 1 0 Transfer Data bytes Figure 5 3-line (8 bit) SPI B mode Timing (A0 is not used)
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"Set No. of Data Bytes" is used in this mode only. It must be 3 continuous instructions with valid data length which informs ST7588T the following n-bytes transfers are display data. After receiving these 3 instructions, the following transfers will be treated as display data until the data length counter is cleared. If data is halted during transmitting, it is not valid data. New data will be transferred serially with most significant bit first. NOTE: In spite of transmission of data, if CSB is disabled, state stops abnormally. Next state is initialized. (2) 3-Line (9-bit) SPI This mode uses the first bit to indicate the following 8 bits are data or instruction.
Figure 6
3-line SPI (9-bit) Timing
I2C Interface The I C interface receives and executes the commands sent via the I C Interface. It also receives display data and sends it to the DDRAM. The I C Interface uses two-line to communicate between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected with a pull-up resistor which drives SDA and SCLK to high when the bus is not busy. Data transfer may be initiated only when the bus is not busy. The I C interface of ST7588T supports write access and checking acknowledge-bit. (1) BIT TRANSFER One data bit is transferred during each clock pulse. Data on the SDA line must remain stable during the HIGH period of the clock pulse, because changes on SDA at this moment will be interpreted as START or STOP. Please refer to Figure 8. (2) START AND STOP CONDITIONS Both SDA and SCLK lines remain HIGH when the bus is ready. A HIGH-to-LOW transition on SDA, while SCLK is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition on SDA, while SCLK is HIGH, is defined as the STOP condition (P). Please refer to Figure 9. (3) SYSTEM CONFIGURATION The system configuration is illustrated in Figure 10. A short glossary is listed below: O O O O O O O Transmitter: the device that sends the data to the bus. Receiver: the device that receives the data from the bus. Master: the device which initiates a transfer, generates clock signals and terminates the transfer. Slave: the device which is addressed by a master. Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message. Arbitration: procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is allowed to do so and the message is not corrupted. Synchronization: procedure to synchronize the clock signals of two or more devices.
2 2 2 2
(4) ACKNOWLEDGE Each byte of eight bits is followed by an acknowledge-bit. The transmitter generates an extra acknowledge-related clock pulse to check the acknowledge-bit. To receive the acknowledge-bit, the transmitter set the SCLK at LOW and put a HIGH signal on SDA. The device that acknowledges must pull-down SDA (acknowledgement) during the acknowledgement clock pulse. The transmitter will check SDA for the acknowledgement. Acknowledge-bit on SDA must be stable LOW during the HIGH period of the acknowledgement clock pulse (set-up and hold times must be taken into consideration). A slave receiver Ver 1.3 23/61 2007/09/20
ST7588T
which is addressed must generate an acknowledge-bit after the reception of each byte. Acknowledgement on the I C Interface is illustrated in Figure 7.
2
Figure 7
Acknowledgement of the I C Interface
2
Figure 8
Bit transfer
Figure 9
Definition of START and STOP conditions
Figure 10 System configuration
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(5) I C Interface protocol 2 The ST7588T supports command/data write addressed slaves on the bus. Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses (011100, 011101, 011110, and 011111) are reserved for the ST7588T. The least significant 2 bits of the slave address is set by connecting SA1 and SA0 to either logic 0 (VSS) or logic 1 (VDD1). The I C Interface protocol is illustrated in Figure 11. A transfer is initiated with a START condition (S) set by the master and followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore this transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co=0). After a control byte with a cleared Co bit, only data bytes will follow. The A0 bit indicates the following data byte is a command or a display data. All addressed slaves on the bus also acknowledge the control and data bytes. The last control byte is followed by either series data bytes with display data or series data bytes with commands (depends on A0 bit). If A0 bit in the last control byte is set to logic 1, these data bytes are display data bytes and will be stored in DDRAM. The data pointer is automatically updated after each display data byte. If A0 bit in the last control byte is set to logic 0, these data bytes are commands and will be decoded to execute the receiving instructions. The master issues a STOP condition (P) at the end of the transmission.
2 2
SA1 SA0
A0
R/W
Co
Co=1 A0
Co
Figure 11 2-line Interface protocol Co 0 1 Last control byte to be sent. Only a stream of data bytes is allowed to follow. This stream may only be terminated by STOP or RE-START condition. Another control byte will follow the data byte unless a STOP or RE-START condition is received.
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Co=0 A0
SA1 SA0 R/W
A0
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ST7588T
Data Transfer
The ST7588T uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 12. Moreover, when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure 13. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signal A0 /WR D0 to D7 Internal signals /WR BUS HOLDER COLUMN ADDRESS N D(N) N D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N D(N) D(N+1) D(N+2) D(N+3)
Figure 12 Write Timing
MPU signal A0 /WR /RD D0 to D7 Internal signals /WR /RD BUS HOLDER COLUMN ADDRESS N N D(N) D(N) D(N+1) D(N+2) D(N+1) D(N+2) N Dummy D(N) D(N+1)
Figure 13 Read Timing
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ST7588T
DISPLAY DATA RAM (DDRAM)
The ST7588T contains an 81X132 bit static RAM that stores the display data. The display data RAM store the dot data for the LCD. It has an 81(10 pageX8 bit +1 pageX1 bit) X 132. There is a direct correspondence between X-address and column output number. It is 81-row by 132-column addressable array. Each pixel can be selected when the page and column addresses are specified.
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 11 is a special RAM area for the icons and display data D0 is only valid.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 132-bit RAM data to the display data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the MPU cannot access Line Address of icons.
Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in Figure 14. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Register MX and MY selection instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing MX select instruction. Refer to the following Figure 15. SEG Output MX "0" "1" Segment Pads SEG0 Seg0 Seg131 Segment Address COM Output MY "0" "1" Common Pads COM0 Com0 Com79 Common Address COM79 a Common Address a Com79 a Com0 a COMS COMS COMS SEG131 a Segment Address a Seg131 Seg0
Data is downloaded in bytes into the RAM matrix of ST7588T as indicated in Figs.14, 15, 16. The display RAM has a matrix of 81 by 132 bits. The address pointer addresses the columns. The address range is: X=0~131 (10000011); Y=0~10 (1010). Addresses out of this range are not allowed. In horizontal addressing mode, the X address increments after each access (see Figure 16). After reaching the last X address (X = 131), X address wraps around to 0 and Y address increases to address the next row. After the very last address (X = 131, Y = 10) the address pointers wrap around to address (X = 0, Y =0)
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ST7588T
Data structure
Figure 14 RAM format and addressing, if DO=0
Figure 15 RAM format and addressing, if DO=1
0
1
2
132 133 134 264 265 266 396 397 398 528 529 530
1188 1189 1190
1319
9 10
0
131
X-address
Figure 16 Sequence of writing data bytes into RAM with horizontal addressing
Ver 1.3
28/61
Y-address
0 1 2 3 4
2007/09/20
ST7588T
LCD DRIVER CIRCUIT
This driver circuit is configured by 81-channel common drivers and 132-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M (Frame Indicator) signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
M
VDD VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0
COM0
COM1
COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
COM2
SEG0
SEG1
SEG 0 1 2 3 4
COM0 to SEG0
COM0 to SEG1
Figure 17 LCD Driver output waveform
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REFERENCE BOOSTER CIRCUIT EXAMPLE
ST7588T
Notes: 1. C1 = 1uF ~ 4.7uF. Please take care about the "Voltage Rating" of the capacitor. 2. VOUT should not exceed the Absolutely Maximum Rating.
ST7588T ST7588T
ST7588T
Figure 18 Booster Configuration
ST7588T
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RESET CIRCUIT
Setting RESB to "L" or Reset instruction can initialize internal function. When RESB becomes "L", the following procedure is entered. Page address: 0 Column address: 0 Display control: Display blank COM Scan Direction MY: 0 SEG Select Direction MX: 0 DO=0 Oscillator: OFF N-line inversion register: 0 (disable) Power down mode (PD = 1) Normal instruction set (H[1:0] = 00) Display blank (E = D = 0) Address counter X [7:0] = 0, Y [3:0] = 0 Bias system (BS [2:0] = 010) V0 is equal to 0; the HV generator is switched off (VOP [6:0] = 0) After power-on, RAM data are undefined While RESB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB0. After DB0 becoming "L", any instruction can be accepted. RESB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESB is essential before used.
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Partial Display on LCD
The ST7588T realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. Moreover, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages.
Figure 20 Reference Example for Partial Display
Figure 21 Partial Display (Partial Display Duty=16, initial COM0=0)
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Figure 22 Moving Display (Partial Display Duty=16, Initial COM0=8)
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n INSTRUCTION TABLE
INSTRUCTION A0 R/W (WR) D7 D7 D7 PD 0 D6 D6 D6 0 0 D5 D5 D5 V 1 COMMAND BYTE D4 D3 D2 D4 D4 D MX D3 D3 E MY D2 D2 MX PD D1 D1 D1 MY H1 D0 D0 D0 DO H0 DESCRIPTION
H independent instruction Write data 1 0 Read data Read status byte Function Set 1 0 0 1 1 0
Write data to RAM Read data to RAM Read status byte Mirror X, Mirror Y, Power Down, Extended table
INSTRUCTION
A0
R/W (WR) 0 0 0 0 0 0 0 0 0 0
D7 0 0 0 0 0 0 0 0 1 1
D6 0 0 0 0 1 1 1 1 1 1
COMMAND BYTE D5 D4 D3 D2 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 DA3 DA7 0 Y3 X3 X7 1 1 1 D DA2 DA6 DA10 Y2 X2 X6
D1 0 1 1 0 DA1 DA5 DA9 Y1 X1 X5
D0
DESCRIPTION
H[1:0]=[0:0] Set V0 (VOP) range 0 END Read/modify/write Display control SI3-8bit data (L)&start SI3-8bit data (M) SI3-8bit data (H) Set Y address Set X Address (L) Set X Address (H) H[1:0]=[0:1] Display configuration Bias system Set V0 (VOP) 0 0 0 0 0 0 0 0 0 0 0 0
PRS V0 (VOP) range L/H select 0 1 E Release read/modify/write RAM address at R:+0 , W:+1
Sets display configuration Set the number of data bytes, DA0 Low-bit (8 bit 3-line SPI) Set the number of data bytes, DA4 Middle-bit (8 bit 3-line SPI) Set the number of data bytes, DA8 High-bit (8 bit 3-line SPI) Y0 X0 X4 Set Y address of RAM 0Y9 Set X address of RAM, Low-bit. 0X131 Set X address of RAM, High-bit. 0X131 Top/bottom row mode set data order
0 0 0 R/W (WR)
0 0 1
0 0 VOP6
0 0 VOP5
0 1 VOP4
1 0 VOP3
DO BS2 VOP2
0 BS1 VOP1
V
BS0 Sets bias system (BSx) VOP0 Write V0 (VOP) to register
INSTRUCTION H[1:0]=[1:0]
A0
COMMAND BYTE D7 D6 D5 D4 D3 D2 D1 D0
DESCRIPTION
Set Partial screen 0 mode Partial Display 0 Set Partial Display 0 part Set Start line H[1:0]=[1:1] RESET High Power Mode Frame N line inversion 0
0 0 0 0
0 0 0 1
0 0 0 S6
0 0 0 S5
0 0 1 S4
0 1 DP3 S3
1 0 DP2 S2
0 0 DP1 S1
PS
PS=1: Enable Partial screen mode.
WS Set partial screen size Set display area for partial DP0 screen mode S0 Specify the initial display line to realize vertical scrolling Software reset
0 0 0 0
0 0 0 0
0 1 0 0
0 0 0 1
0 1 0 0
0 1 0 NL4
0 0 1 NL3
0 HP FR2 NL2
1 0 FR1 NL1
1
0 High Power Mode SET FR0 Frame rate control NL0 Sets N line inversion
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n INSTRUCTION DESCRIPTION
H[1:0] independent
Write data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. D7 D6 D5 D4 D3 D2 D1 D0 A0 WR(R/W) 0 0 Write data
Read data
8-bit data of Display Data from the RAM location specified by the column address and page address can be read to the microprocessor. A0 1 WR(R/W) 1 D7 D6 D5 D4 D3 Read data D2 D1 D0
Read status byte
Indicates the internal status of the ST7588T D7 D6 A0 WR(R/W) 0 Flag PD V 1 PD 0 D5 V D4 D D3 E D2 MX D1 MY D0 DO
Description PD=0:chip is active PD=1:chip is in power down mode When V = 0, the horizontal addressing is selected. When V = 1, the vertical addressing is selected. D 0 E The bits D and E select the display mode. 0 Display OFF 1 All display segments on 0 Normal mode
D,E
0 1
MX
1 1 Inverse video mode SEG bi-direction selection MY=0:normal direction (SEG0(SEG131) MY=1:reverse direction (SEG131(SEG0) COM bi-direction selection MY=0:normal direction (COM0(COM79) MY=1:reverse direction (COM79(COM0) DO=0:MSB is on top DO=1:LSB is on top WR(R/W) 0 D7 0 D6 0 D5 1 D4 MX Description SEG bi-direction selection MY=0:normal direction (SEG0aSEG131); MY=1:reverse direction (SEG131aSEG0) COM bi-direction selection MY=0:normal direction (COM0aCOM79); MY=1:reverse direction (COM79aCOM0) PD=0:chip is active; PD=1:chip is in power down mode All LCD outputs at VSS (display off), bias generator and VOUT generator off, V0 can be disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data can be written. Selection of Extended Command Table D3 MY D2 PD D1 H1 D0 H0
MY
DO
Function Set
A0 0 Flag MX MY
PD
H0, H1
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H[1:0]=[0:0]
Set V0 (VOP) range
V0 (VOP) range L/H select D7 A0 WR(R/W) D6 D5 0 D4 0 D3 0 D2 1 D1 0 D0 PRS
0 0 0 0 PRS=0: V0 (VOP) programming range LOW PRS=1: V0 (VOP) programming range HIGH
END
This command releases the read/modify/write mode, and returns the column and row address to the address it was at when the mode was entered. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 0
Read/modify/write
This command is used coupled with the "END" command. Once this command has been input, the display data read command does not change the column and row address, but only the display data write command increments (+1) the address depend on V register setting. This mode is kept until the END command is input. When the END command is input, the address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. A0 0 WR(R/W) 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 1 D0 1
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
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Display Control
This bits D and E selects the display mode. A0 WR(R/W) D7 D6 0 0 0 0 Flag D 0 D,E 1 0 1 D5 0 D4 0 Description E The bits D and E select the display mode. 0 Display OFF 0 Normal display 1 All display segments on 1 Inverse video mode D3 1 D2 D D1 0 D0 E
Set SI3-8 bit Data Display Data Length resister
This command is used in 8-bit 3-line SPI only. When A0 is not used, the Display Data Length instruction is used to indicate the specified number of display data byte to be transmitted. The next byte after the display data string is handled as data. A0 0 0 0 DA10 0 0 0 : 1 1 1 1 WR (R/W) 0 0 0 DA9 0 0 0 : 0 0 0 0 D7 0 0 0 DA8 0 0 0 : 1 1 1 1 D6 1 1 1 DA7 0 0 0 : 0 0 0 0 D5 0 1 1 DA6 0 0 0 : 0 0 0 0 D4 1 0 1 DA5 0 0 0 : 1 1 1 1 D3 DA3 DA7 0 DA4 0 0 0 : 0 0 0 0 D2 DA2 DA6 DA10 DA3 0 0 0 : 0 0 0 1 D1 DA1 DA5 DA9 DA2 0 0 0 : 1 1 1 0 D0 DA0 DA4 DA8 DA1 0 0 1 : 0 1 1 0 DA0 0 1 0 : 1 0 1 0 Description SPI3-8bit Data(L) & Start SPI3-8bit Data(M) SPI3-8bit Data(H) Display Data Length 1 2 3 : 1317 1318 1319 1320
Set Y address of RAM
Y [3:0] defines the Y address vector address of the display RAM. A0 0 Y3 0 0 0 0 0 0 0 0 1 1 Y2 0 0 0 0 1 1 1 1 0 0 WR(R/W) 0 Y1 0 0 1 1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 0 1 0 1 D7 0 D6 1 CONTENT Page0 (display RAM) Page1 (display RAM) Page2 (display RAM) Page3 (display RAM) Page4 (display RAM) Page5 (display RAM) Page6 (display RAM) Page7 (display RAM) Page8 (display RAM) Page9 (display RAM) D5 0 D4 0 D3 Y3 D2 Y2 D1 Y1 D0 Y0
ALLOWED X-RANGE 0 to 131 0 to 131 0 to 131 0 to 131 0 to 131 0 to 131 0 to 131 0 to 131 0 to 131 0 to 131
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Set X address of RAM
The X address points to the columns. The range of X is 0...131. WR A0 D7 D6 D5 (R/W) Set X Address (Low) Set X address (High) X7 0 0 0 0 : 1 1 1 1 X6 0 0 0 0 : 0 0 0 0 X5 0 0 0 0 : 0 0 0 0 0 0 X4 0 0 0 0 : 0 0 0 0 0 0 1 1 X3 0 0 0 0 : 0 0 0 0 1 1 X2 0 0 0 0 : 0 0 0 0 1 1 X1 0 0 1 1 : 0 0 1 1 D4 0 1 X0 0 1 0 1 : 0 1 0 1 D3 X3 X7 D2 X2 X6 D1 X1 X5 D0 X0 X4
Column address 0 1 2 3 : 128 129 130 131
H[1:0]=[0:1]
Display configuration
Top/bottom row mode set data order and the direction of Address. A0 WR(R/W) D7 D6 D5 D4 D3 0 Flag DO V 0 0 0 0 0 1 D2 DO D1 0 D0 V
Description DO=0:MSB is on top DO=1:LSB is on top When V = 0, the horizontal addressing is selected. When V = 1, the vertical addressing is selected.
System Bias
Select LCD bias ratio of the voltage required for driving the LCD. A0 WR(R/W) D7 D6 D5 D4 D3 0 0 0 0 0 1 0 BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 Bias 11 10 9 8 7 6 5 4 D2 BS2 D1 BS1 D0 BS0
LCD bias voltage
Symbol V0 V1 V2 Bias voltage for 1/9 bias V0 8/9 X V0 7/9 X V0 Symbol V3 V4 VSS Bias voltage for 1/9 bias 2/9 X V0 1/9 X V0 VSS
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Set V0 (VOP) value:
A0 0 WR(R/W) 0 D7 1 D6 VOP6 D5 VOP5 D4 VOP4 D3 VOP3 D2 VOP2 D1 VOP1 D0 VOP0
The operation voltage V0 (VOP) can be set by software. V0 = VOP = ( a + VOP x b ) (1)
The parameters are described in table 4.The maximum voltage that can be generated is depending on the VDD1 voltage and the display load current. Two overlapping V0 (VOP) ranges are selectable via the command "Booster control". For the LOW (PRS=0) range a=a1 and for the HIGH (PRS=1) range a=a2 with steps equal to "b" in both ranges. Note that the charge pump is turned off if VOP [6;0] and the bit PRS are all set to zero. SYMBOL a1 a2 b Table 4
V0
VALUE 3.528(PRS=0) 8.862(PRS=1) 0.042
UNIT V V V
Typical values for parameter for the HV-Generator programming
b
Charge pump off
a2 a1+b 01 02 03 04 05 06 ..... 7D 7E 7F 00 01 02 03 04 05 06 ..... 7D 7E 7F
00
Lower Range (PRS=0)
Higher Range (PRS=1)
VOP [6:0] (0x00~0x7F} Figure 23 V0 (VOP) programming of ST7588T
* Recommended LCD VOP voltage is 9.5V~10.5V (1/10 Bias).
H[1:0]=[1:0]
Partial screen mode
A0 0 Flag PS WR(R/W) 0 D7 0 D6 0 D5 0 D4 0 Description Full display mode or partial screen mode selection. PS=0:Full display mode with MUX 1:80. PS=1:Partial screen mode with MUX 1:16 or MUX 1:32. D3 0 D2 1 D1 0 D0 PS
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Partial screen size
This instruction controls partial screen size, partial screen 16 rows when WS is low and partial screen 32 rows when WS is high. D7 D6 D5 D4 D3 D2 D1 D0 A0 WR(R/W) 0 0 0 0 0 0 1 0 0 WS
Display part
This instruction can select partial screen display area. A0 WR(R/W) D7 D6 D5 0 (1) 1/16 Duty Flag 0 0 0 DP3 DP2 DP1 DP0 0 0 0 0 0 1 1 (2) 1/32 Duty Flag 0 0 0 DP3 DP2 DP1 DP0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 Status 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Description RAM bank 0 to 3 (row0~row31) RAM bank 1 to 4 (row8~row39) RAM bank 2 to 5 (row16~row47) RAM bank 3 to 6 (row24~row55) RAM bank 4 to 7 (row32~row63) RAM bank 5 to 8 (row40~row71) RAM bank 6 to 9 (row48~row79) RAM bank 7 to 9 (row56~row79) RAM bank 8 to 9 (row64~row79) RAM bank 9 (row72~row79) 0 0 0 0 1 1 1 1 0 0 Status 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Description RAM bank 0 to 1 (row0~row15) RAM bank 1 to 2 (row8~row23) RAM bank 2 to 3 (row16~row31) RAM bank 3 to 4 (row24~row39) RAM bank 4 to 5 (row32~row47) RAM bank 5 to 6 (row40~row55) RAM bank 6 to 7 (row48~row63) RAM bank 7 to 8 (row56~row71) RAM bank 8 to 9 (row64~row79) RAM bank 9 (row72~row79) 0 0 0 0 D4 1 D3 DP3 D2 DP2 D1 DP1 D0 DP0
Set start line
Sets the line address of display RAM to determine the initial display line instruction. The RAM display data is displayed at the top of row (COM0) of LCD panel. A0 0 S6 0 0 0 0 : 1 1 1 WR(R/W) 0 S5 0 0 0 0 : 0 0 0 D7 1 S4 0 0 0 0 : 0 0 0 D6 S6 S3 0 0 0 0 : 1 1 1 D5 S5 S2 0 0 0 0 : 1 1 1 D4 S4 D3 S3 S1 0 0 1 1 : 0 1 1 D2 S2 S0 0 1 0 1 : 1 0 1 D1 S1 D0 S0 Line address 0 1 2 3 : 77 78 79
Note: when 81 duty is selected, 4f (1001111) is MAX; when 65 duty is selected, 3f (0111111) is MAX; when 49 duty is selected, 2f (0101111) is MAX Ver 1.3 40/61 2007/09/20
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H[1:0]=[1:1]
Reset
This instruction resets initial display line, column address, page address, and common output status select to their initial status .This instruction cannot initialize the LCD power supply, which is initialized by the RESB pin. A0 0 WR(R/W) 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1
High Power Mode
This command is to enter the high power mode. HP=1: high power mode, HP=0: normal mode. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 0 0 1 0 1 1 0 HP 0 D0 0
Frame frequency
A0 0 WR(R/W) 0 D7 0 D6 0 D5 0 D4 0 D3 1 D2 FR2 D1 FR1 D0 FR0
This command is used to set the frame frequency. FR2 0 0 0 0 1 1 1 1 FR1 0 0 1 1 0 0 1 1 FR0 0 1 0 1 0 1 0 1 Frame frequency 50 Hz 68 Hz 70 Hz 73 Hz 75 Hz 78 Hz 81 Hz 150 Hz
Set N-line inversion
Sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the phase of the internal LCD AC signal (M) Note: The N-line inversion mode will be disabled when partial display mode enter. After the partial display mode end, the N-line inversion mode will return as it was. A0 0 NL4 0 0 0 0 : 1 1 1 WR(R/W) 0 NL3 0 0 0 0 : 1 1 1 D7 0 NL2 0 0 0 0 : 1 1 1 D6 1 NL1 0 0 1 1 : 0 1 1 D5 0 D4 NL4 NL0 0 1 0 1 : 1 0 1 D3 NL3 D2 NL2 D1 NL1 D0 NL0
Selected n-line inversion Frame inversion 3-line inversion 4-line inversion 5-line inversion : 31-line inversion 32-line inversion 33-line inversion
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n COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
Figure 24 Initializing with the Built-in Power Supply Circuits
Referential Instruction Flow for Power Down:
Function set PD=0, H1=0, H0=1 Set V0 (VOP)=0 Function set PD=0, H1=0, H0=0 Set PRS=0
Function set PD=0, H1=1, H0=1 Write Command #10100001B [command for discharge] Function set PD=1, H1=1, H0=1 [Power Down Mode] Delay 250ms Write Command #10100000B [discharge process finished]
Power Down Mode Entered
Figure 25 Instruction Flow for Power Down
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n ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Digital Power Supply Voltage Analog Power supply voltage LCD Operation Power supply voltage LCD Driving Power supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD1 VDD2 VOUT, V0 V1, V2, V3, V4 VIN VO TOPR TSTR Conditions -0.3 ~ 3.6 -0.3 ~ 3.6 -0.5 ~ +13.5 0.3 to V0 -0.5 to VDD+0.5 -0.5 to VDD+0.5 -30 to +85 -65 to +150 Unit V V V V V V C C
Notes 1. 2. 3. 4. Stresses above those listed under Limiting Values may cause permanent damage to the device. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VOUT V0 V1 V2 V3 V4 Vss Recommended LCD VOP voltage is 9.5V~10.5V (1/10 Bias).
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n DC CHARACTERISTICS
VSS = 0V; Tamb = -30 to +85; unless otherwise specified. Item Symbol Condition Rating Min. 1.8 Typ. -Max. 3.3 Units Applicable Pin VDD1
Operating Voltage (1)
VDD1
V
Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Liquid Crystal Driver ON
VDD2 VIHC VILC VOHC VOLC ILI RON IOH=1mA IOL=1mA VIN = VDD1 or VSS Ta = 25C (relative to VSS) V0 = 11.0 V
2.4 0.7 x VDD1 VSS 0.8 x VDD1 VSS -1.0 --
------0.8
3.3 VDD1 0.3 x VDD1 VDD1 0.2 x VDD1 1.0 1.1
V V V V V A k
VDD2
SEGn COMn *1
Resistance Internal Oscillator Frequency Oscillator Frame Frequency
fOSC 1/81 duty fFRAME
---
50 75
---
kHz Hz
Item Internal Power Voltage Step-up Circuit output
Symbol
Condition
Rating Min. -Typ. -Max. 13.5
Units
Applicable Pin VSS, *2
VOUT
(Relative To VSS)
V
* Recommended LCD VOP voltage is 9.5V~10.5V (1/10 Bias). Dynamic Consumption Current: During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used. Test pattern Display Pattern SNOW Power Down 1. 2. 3. 4. Internal clock The maximum possible VOUT voltage that may be generated is dependent on voltage, temperature and (display) load. If external V0 used, the display load current is not transmitted to I DD. Power-down mode. During power down, all static currents are switched off. Symbol ISS ISS Condition VDD = 3.0 V, V0 - VSS = 10.0 V Ta = 25C Min. --Rating Typ. 120 0.05 Max. -2 Units A A Notes *3 *4
Notes to the DC characteristics:
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n TIMING CHARACTERISTICS
System Bus Read/Write Characteristics (For the 8080 Series MPU)
Figure 26 (VDD = 3.3V, Ta = -30 to 85 C) Item Address hold time Address setup time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Data hold time (Write) Data access time (Read) Output disable time (Read) D[7:0] /WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 20 20 80 70 30 90 30 80 20 -10 Max. ---------50 30 ns Units
/RD
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(VDD = 2.7V, Ta = -30 to 85 C) Item Address hold time Address setup time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Data hold time (Write) Data access time (Read) Output disable time (Read) D[7:0] /WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 20 20 90 80 30 110 30 90 20 -10 Max. ---------60 40 ns Units
/RD
(VDD = 1.8V, Ta = -30 to 85 C) Item Address hold time Address setup time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Data hold time (Write) Data access time (Read) Output disable time (Read) 1. 2. 3. D[7:0] /WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 20 20 220 200 30 220 30 220 20 -10 Max. ---------100 30 ns Units
/RD
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. All timing is specified using 20% and 80% of VDD as the reference. tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics (For the 6800 Series MPU)
Figure 27 (VDD = 3.3V, Ta = -30 to 85 C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 20 60 100 30 40 30 40 70 20 -10 Max. ---------70 40 ns Units
RD
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(VDD = 2.7V, Ta = -30 to 85 C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 20 70 140 30 40 30 40 90 20 -10 Max. ---------80 40 ns Units
RD
(VDD = 1.8V, Ta = -30 to 85 C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time 1. 2. 3. D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 20 80 270 40 60 40 70 210 20 -10 Max. ---------80 40 ns Units
RD
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. All timing is specified using 20% and 80% of VDD as the reference. tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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SERIAL INTERFACE (I C Interface)
2
Figure 28 (VDD = 3.3V, Ta = -30 to 85 C) Item SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time Setup time for a repeated START condition Start condition hold time Setup time for STOP condition BUS free time between a STOP and START condition SCL Signal SCL SCL SCL SDA SDA SDA SDA Symbol fSCLK tLOW tHIGH tSU;Dat tHD;Dat tSU;STA tHD;STA tSU;STO tBUF Condition Rating Min. DC 150 100 90 40 70 170 90 70 Max. 400 --------ns Units kHz
(VDD = 2.7V, Ta = -30 to 85 C) Item SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time Setup time for a repeated START condition Start condition hold time Setup time for STOP condition BUS free time between a STOP and START condition SCL Signal SCL SCL SCL SDA SDA SDA SDA Symbol fSCLK tLOW tHIGH tSU;Dat tHD;Dat tSU;STA tHD;STA tSU;STO tBUF Condition Rating Min. DC 190 110 110 30 90 220 110 90 Max. 400 --------ns Units kHz
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SERIAL INTERFACE (4-Line Interface)
First bit
Figure 29
Last bit
(VDD = 3.3V, Ta = -30 to 85 C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 100 60 60 20 80 20 20 30 120 Max. ---------ns Units
SDA
CSB
(VDD = 2.7V, Ta = -30 to 85 C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 120 70 70 20 100 20 20 30 150 Max. ---------ns Units
SDA
CSB
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(VDD = 1.8V, Ta = -30 to 85 C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time 1. 2. A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 330 150 150 20 160 40 40 40 370 Max. ---------ns Units
SDA
CSB
The input signal rise and fall time (tr, tf) are specified at 15 ns or less. All timing is specified using 20% and 80% of VDD as the standard.
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SERIAL INTERFACE (3-Line Interface)
First bit
Figure 30
Last bit
(VDD = 3.3V, Ta = -30 to 85 C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SDA SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 100 60 60 20 20 30 120 Max. -------ns Units
CSB
(VDD = 2.7V, Ta = -30 to 85 C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SDA SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 120 70 70 20 20 30 150 Max. -------ns Units
CSB
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(VDD = 1.8V, Ta = -30 to 85 C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time 1. 2. SDA SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 330 150 150 40 40 40 370 Max. -------ns Units
CSB
The input signal rise and fall time (tr, tf) are specified at 15 ns or less. All timing is specified using 20% and 80% of VDD as the standard.
n RESET TIMING
tRW
RESB
tR
Internal Status
During Reset ...
Figure 31
Reset Finished
(VDD = 3.3V, Ta = -30 to 85 C) Item Reset time Reset "L" pulse width /RES Signal Symbol tR tRW Condition Rating Min. -1200 Typ. --Max. 400 -Units
ns
(VDD = 2.7V, Ta = -30 to 85 C) Item Reset time Reset "L" pulse width /RES Signal Symbol tR tRW Condition Rating Min. -1600 Typ. --Max. 350 -Units
ns
(VDD = 1.8V, Ta = -30 to 85 C) Item Reset time Reset "L" pulse width /RES Signal Symbol tR tRW Condition Rating Min. -4500 Typ. --Max. 140 -Units
ns
Ver 1.3
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ST7588T
n THE MPU INTERFACE (REFERENCE EXAMPLES)
ST7588T can be connected to either 80X86 Series MPU or to 6800 Series MPU. (1) 8080 Series MPU
VDD VCC A0 A1 to A7 IORQ DO to D7 RD WR RES RESET Decoder A0 CSB VDD PS2 PS1 PS0 ST7588T
MPU
GND
D0 to D7 /RD (E) /WR (R/W) /RES VSS
VSS
(2) 6800 Series MPU
VDD VCC A0 A1 to A7 IORQ DO to D7 RD WR RES RESET Decoder A0 CSB D0 to D7 E (/RD) R/W (/WR) /RES VSS VDD PS0 PS1 PS2 ST7588T
MPU GND
VSS
(3) Using the Serial Interface (4-line interface A mode)
VDD VCC A0 A1 to A7 MPU Decoder A0 CSB VDD PS0 PS1 PS2 ST7588T VSS VSS
Port 1 Port 2 RES GND RESET
SDA SCL /RES
Ver 1.3
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ST7588T
(4) Using the Serial Interface (4-line interface B mode)
VDD VCC A0 A1 to A7 MPU Decoder A0 CSB VDD PS2 PS1 PS0 ST7588T VSS VSS
Port 1 Port 2 RES GND RESET
SDA SCL /RES
(5) Using the Serial Interface (3-line interface 8 bit A mode)
VDD VCC VDD PS2 PS1 PS0 ST7588T VSS VSS
(6) Using the Serial Interface (3-line interface 8 bit B mode)
A1 to A7 MPU
Decoder
CSB
Port 1 Port 2 RES GND RESET
SDA SCL /RES
VDD VCC VDD PS0 PS1 PS2 ST7588T VSS VSS
A1 to A7 MPU
Decoder
CSB
Port 1 Port 2 RES GND RESET
SDA SCL /RES
Ver 1.3
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ST7588T
(7) Using the Serial Interface (3-line interface 9 bit)
VDD VCC VDD PS2 PS1 PS0 ST7588T VSS VSS
A1 to A7 MPU
Decoder
CSB
Port 1 Port 2 RES GND RESET
SDA SCL /RES
(8) Using the Serial Interface (I C interface)
VDD VCC VDD PS0 PS1 PS2 Port 1 Port 2 RES RESET GND VSS VSS SDA SCL /RES ST7588T
2
Ver 1.3
MPU
56/61
2007/09/20
ST7588T
n APPLICATION CIRCUITS
For the 6800 interface & 32 duty (partial display)
~
COM37 COM39
SEG131
COMS2 V4 V3 V2 V1 V0 VRS CAP4P CAP4P CAP2N CAP2N CAP2P CAP2P CAP1P CAP1P CAP1N CAP1N CAP5P CAP5P CAP3P CAP3P CAP3N CAP3N VOUT VOUT VOUT VDD2 VDD2 VDD VDD VDD PS2 PS1 PS0 MODE1 MODE0 MS VSS VSS VSS T0 T1 T2 T3 T4 T5 D7 D6 D5 D4 D3 D2 D1 D0 /RD(E) /WR(R/W) A0 RESB VSS CSB DOF CL SYNC
SEG0 COMS1
COM8 COM10
~
Ver 1.3
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ST7588T
For the 4-line A interface & 65 duty
Ver 1.3
58/61
2007/09/20
ST7588T
For the 3-line 9 bit interface & 49 duty
~
COM37
SEG131
COM47 COMS2 V4 V3 V2 V1 V0 VRS CAP4P CAP4P CAP2N CAP2N CAP2P CAP2P CAP1P CAP1P CAP1N CAP1N CAP5P CAP5P CAP3P CAP3P CAP3N CAP3N VOUT VOUT VOUT VDD2 VDD2 VDD VDD VDD PS2 PS1 PS0 MODE1 MODE0 MS VSS VSS VSS T0 T1 T2 T3 T4 T5 D7 D6 D5 D4 D3 D2 D1 D0 /RD(E) /WR(R/W) A0 RESB VSS CSB DOF CL SYNC
SEG0 COMS1 COM0
COM10
~
Ver 1.3
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ST7588T
For the I C interface & 81 duty
In I C application, be awarded that the impedance of SDAs and GNDs should be treated as the POWER PIN.
2
2
~
COM51 COM69
COM40 SEG131
COM79 COMS2 V4 V3 V2 V1 V0 VRS CAP4P CAP4P CAP2N CAP2N CAP2P CAP2P CAP1P CAP1P CAP1N CAP1N CAP5P CAP5P CAP3P CAP3P CAP3N CAP3N VOUT VOUT VOUT VDD2 VDD2 VDD VDD VDD PS2 PS1 PS0 MODE1 MODE0 MS VSS VSS VSS T0 T1 T2 T3 T4 T5 D7 D6 D5 D4 D3 D2 D1 D0 /RD(E) /WR(R/W) A0 RESB VSS CSB DOF CL SYNC COM39
SEG0 COMS1 COM0
COM10
COM28
~
Ver 1.3
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ST7588T
n REVERSION HISTORY
Version 1.0 Data 2005/08/01 1. 2. 1. 2. 3. 4. 1. 1. 1. 2. 3. 4. 5. Remove "Preliminary". 2 Update I C SCL clock frequency. Chip thickness. Redraw some figures. Bias default value BS[2:0]=010. Update VDD2 range. Remove History before V1.0. Add voltage endurance warning to Booster Connection. Fix description mistake. Remove Master-Slave related sections. Master-Slave function is reserved for special specification by customer. Redraw timing figures. 2 Remove I C timing at 1.8V. Fix Power Save flow mistake. Description
1.1
2005/11/11
1.2 1.2a
2005/12/22 2005/12/29
1.3
2007/09/20
Ver 1.3
61/61
2007/09/20

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